1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the control of clock signals within such data processing systems.
2. Description of the Prior Art
Data processing systems include clock signals that control, regulate and drive many of the operations of the data processing apparatus. The frequency of the clock signal that is used is often a determining factor in the overall system performance since a given data processing operation may be constrained to take a fixed number of clock cycles rather than a particular time period. Accordingly, it is desirable to use as fast a clock signal as possible.
A problem with fast clock signals is that they result in an increase in power consumption. Even within the small physical size of an integrated circuit, the circuit elements and interconnecting lines have a finite capacitance resulting in a significant current flow, and consequential power consumption, as these elements and lines follow the controlling clock signal potential. This increase in power consumption within integrated circuits leads to a number of problems, e.g. potentially destructive circuit heating that requires additional heat dissipation measures to overcome.
A particular conflict between the desire for high clock speeds and other considerations arises in the field of small portable devices. With these devices available battery power is often a significant limitation and so any measures that can reduce power consumption whilst maintaining system performance are strongly advantageous.
In view of the above, specific integrated circuits have been designed for use in portable computers that allow the clock speed to be selected between a high clock speed used when significant data processing activity is required and a much lower clock speed for use when the required amount of data processing is low, e.g. the system is waiting for an input from elsewhere, such as a user input.
Whilst selectable clock speed reduces average power consumption, further reduction is advantageous.
It has been proposed in European Published Patent Application EP-A-0 562 885 to provide a system in which the clock signal supplied to a central processing unit may be stopped in certain circumstances. In this proposed system, the central processing unit has within its instruction set a HALT instruction which acts as a busy wait state in which the clock signal is usually maintained but processing does not progress any further until an interrupt occurs.
The system proposed in EP-A-0 562 885 adds additional circuitry that detects the occurrence of such HALT commands and responds by disabling the supply of the clock signal to portions of the circuit. Thus, for those portions, the clock is stopped rather than merely slowed and an improved power consumption saving is made.
The proposed system of EP-A-0 562 885 suffers from a number of disadvantages. The system proposed in EP-A-0 562 885 assumes the existence of a HALT command within the central processing unit instruction set. Whilst the provision of such a command is not a problem when operating in a complex instruction set computing (CISC) environment, when operating in a reduced instruction set computing (RISC) environment it is disadvantageous to increase the overall size of the instruction set.
A further disadvantage of the system of EP-A-0 562 885 is that it relies upon the occurrence of interrupt signals to exit from the mode in which the clock is stopped. Interrupt signals have associated with them various interrupt handling routines and it is a disadvantageous constraint to always have to execute such an exception handling routine when restarting the clock signal. Furthermore, the need to have an interrupt to exit the clock stopped mode limits the circumstances in which the technique may be used.
It is an object of the invention to address the abovementioned problems.